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clk: amlogic: introduce a common pclk definition

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All Amlogic peripheral clocks are more or less the same. The only thing
that differs is the parent data.

Adapt the common pclk definition so it takes clk_parent_data and can be
used by all controllers.

Reviewed-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-8-0f402f01e117@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Jerome Brunet
2025-08-25 16:26:33 +02:00
parent c3f369363a
commit aaee6f3bce
7 changed files with 52 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/meson/a1-peripherals.c
View File

@@ -1840,8 +1840,10 @@ static struct clk_regmap a1_cecb_32k_out = {
},
};
static const struct clk_parent_data a1_pclk_parents = { .hw = &a1_sys.hw };
#define A1_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags)
MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags)
/*
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons

4
drivers/clk/meson/axg.c
View File

@@ -1915,8 +1915,10 @@ static struct clk_regmap axg_gen_clk = {
},
};
static const struct clk_parent_data axg_pclk_parents = { .hw = &axg_clk81.hw };
#define AXG_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags)
MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags)
/*
* Everything Else (EE) domain gates

6
drivers/clk/meson/g12a.c
View File

@@ -4384,11 +4384,13 @@ static struct clk_regmap sm1_nna_core_clk = {
},
};
static const struct clk_parent_data g12a_pclk_parents = { .hw = &g12a_clk81.hw };
#define G12A_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags)
MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags)
#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \
MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags)
MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags)
/*
* Everything Else (EE) domain gates

26
drivers/clk/meson/gxbb.c
View File

@@ -2721,8 +2721,10 @@ static struct clk_regmap gxbb_gen_clk = {
},
};
static const struct clk_parent_data gxbb_pclk_parents = { .hw = &gxbb_clk81.hw };
#define GXBB_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags)
MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags)
/*
* Everything Else (EE) domain gates
@@ -2817,14 +2819,20 @@ static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED);
static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED);
/* AIU gates */
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IGNORE_UNUSED);
static const struct clk_parent_data gxbb_aiu_glue_parents = { .hw = &gxbb_aiu.hw };
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parents, CLK_IGNORE_UNUSED);
static const struct clk_parent_data gxbb_aiu_pclk_parents = { .hw = &gxbb_aiu_glue.hw };
#define GXBB_AIU_PCLK(_name, _bit, _flags) \
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags)
static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED);
static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED);
/* Array of all clocks provided by this provider */

12
drivers/clk/meson/meson-clkc-utils.h
View File

@@ -27,7 +27,7 @@ struct meson_clkc_data {
int meson_clkc_syscon_probe(struct platform_device *pdev);
int meson_clkc_mmio_probe(struct platform_device *pdev);
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \
#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \
struct clk_regmap _name = { \
.data = &(struct clk_regmap_gate_data) { \
.offset = (_reg), \
@@ -36,16 +36,16 @@ struct clk_regmap _name = { \
.hw.init = &(struct clk_init_data) { \
.name = #_name, \
.ops = _ops, \
.parent_hws = (const struct clk_hw *[]) { _pname }, \
.parent_data = (_pdata), \
.num_parents = 1, \
.flags = (_flags), \
}, \
}
#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags)
#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags)
#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags)
#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \
__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags)
#endif

27
drivers/clk/meson/meson8b.c
View File

@@ -2701,8 +2701,10 @@ static struct clk_regmap meson8b_cts_i958 = {
},
};
static const struct clk_parent_data meson8b_pclk_parents = { .hw = &meson8b_clk81.hw };
#define MESON8B_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags)
MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags)
/*
* Everything Else (EE) domain gates
@@ -2785,18 +2787,21 @@ static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED);
static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED);
/* AIU gates */
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CLK_IGNORE_UNUSED);
static const struct clk_parent_data meson8b_aiu_glue_parents = { .hw = &meson8b_aiu.hw };
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6,
&meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED);
#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags)
static const struct clk_parent_data meson8b_aiu_pclk_parents = { .hw = &meson8b_aiu_glue.hw };
#define MESON8B_AIU_PCLK(_name, _bit, _flags) \
MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags)
static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_UNUSED);
static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED);
static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED);
/* Always On (AO) domain gates */

4
drivers/clk/meson/s4-peripherals.c
View File

@@ -3165,8 +3165,10 @@ static struct clk_regmap s4_gen_clk = {
},
};
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
#define S4_PCLK(_name, _reg, _bit, _flags) \
MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags)
MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags)
/*
* NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons