timers/migration: Add mask for CPUs available in the hierarchy

Keep track of the CPUs available for timer migration in a cpumask. This
prepares the ground to generalise the concept of unavailable CPUs.

Signed-off-by: Gabriele Monaco <gmonaco@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251120145653.296659-3-gmonaco@redhat.com
This commit is contained in:
Gabriele Monaco
2025-11-20 15:56:48 +01:00
committed by Thomas Gleixner
parent 8312cab5ff
commit a048ca5f00

View File

@@ -424,6 +424,12 @@ static struct tmigr_group *tmigr_root;
static DEFINE_PER_CPU(struct tmigr_cpu, tmigr_cpu);
/*
* CPUs available for timer migration.
* Protected by cpuset_mutex (with cpus_read_lock held) or cpus_write_lock.
*/
static cpumask_var_t tmigr_available_cpumask;
#define TMIGR_NONE 0xFF
#define BIT_CNT 8
@@ -1433,6 +1439,7 @@ static int tmigr_clear_cpu_available(unsigned int cpu)
int migrator;
u64 firstexp;
cpumask_clear_cpu(cpu, tmigr_available_cpumask);
raw_spin_lock_irq(&tmc->lock);
tmc->available = false;
WRITE_ONCE(tmc->wakeup, KTIME_MAX);
@@ -1446,7 +1453,7 @@ static int tmigr_clear_cpu_available(unsigned int cpu)
raw_spin_unlock_irq(&tmc->lock);
if (firstexp != KTIME_MAX) {
migrator = cpumask_any_but(cpu_online_mask, cpu);
migrator = cpumask_any(tmigr_available_cpumask);
work_on_cpu(migrator, tmigr_trigger_active, NULL);
}
@@ -1461,6 +1468,7 @@ static int tmigr_set_cpu_available(unsigned int cpu)
if (WARN_ON_ONCE(!tmc->tmgroup))
return -EINVAL;
cpumask_set_cpu(cpu, tmigr_available_cpumask);
raw_spin_lock_irq(&tmc->lock);
trace_tmigr_cpu_available(tmc);
tmc->idle = timer_base_is_idle();
@@ -1805,6 +1813,11 @@ static int __init tmigr_init(void)
if (ncpus == 1)
return 0;
if (!zalloc_cpumask_var(&tmigr_available_cpumask, GFP_KERNEL)) {
ret = -ENOMEM;
goto err;
}
/*
* Calculate the required hierarchy levels. Unfortunately there is no
* reliable information available, unless all possible CPUs have been