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pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu

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For i.MX8MQ platform, the ADB in the VPUMIX domain has no separate reset
and clock enable bits, but is ungated and reset together with the VPUs.
So we can't reset G1 or G2 separately, it may led to the system hang.
Remove rst_mask and clk_mask of imx8mq_vpu_blk_ctl_domain_data.
Let imx8mq_vpu_power_notifier() do really vpu reset.

Fixes: 608d7c325e ("soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl")
Signed-off-by: Ming Qian <ming.qian@oss.nxp.com>
Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ming Qian
2025-12-05 09:54:25 +08:00
committed by Ulf Hansson
parent 73cb5f6eaf
commit 3de4996649
1 changed files with 7 additions and 4 deletions
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11
drivers/pmdomain/imx/imx8m-blk-ctrl.c
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@@ -846,22 +846,25 @@ static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
/*
* For i.MX8MQ, the ADB in the VPUMIX domain has no separate reset and clock
* enable bits, but is ungated and reset together with the VPUs.
* Resetting G1 or G2 separately may led to system hang.
* Remove the rst_mask and clk_mask from the domain data of G1 and G2,
* Let imx8mq_vpu_power_notifier() do really vpu reset.
*/
static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
[IMX8MQ_VPUBLK_PD_G1] = {
.name = "vpublk-g1",
.clk_names = (const char *[]){ "g1", },
.num_clks = 1,
.gpc_name = "g1",
.rst_mask = BIT(1),
.clk_mask = BIT(1),
},
[IMX8MQ_VPUBLK_PD_G2] = {
.name = "vpublk-g2",
.clk_names = (const char *[]){ "g2", },
.num_clks = 1,
.gpc_name = "g2",
.rst_mask = BIT(0),
.clk_mask = BIT(0),
},
};